Semiconductor intellectual property core

Results: 98



#Item
11REAL-TIME STITCHING IP MAKES 360-DEGREE VIDEOS April 13, By Peter Clarke Embedded systems design consultancy Argon Design Ltd. (Cambridge, England) has created prototype hardware that can stitch together video st

REAL-TIME STITCHING IP MAKES 360-DEGREE VIDEOS April 13, By Peter Clarke Embedded systems design consultancy Argon Design Ltd. (Cambridge, England) has created prototype hardware that can stitch together video st

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Source URL: www.argondesign.com

Language: English - Date: 2016-05-03 06:50:07
12OpenCores HDL modeling guidelines This document describes the OpenCores HDL modelling guidelines with some examples Brought to You By OpenCores

OpenCores HDL modeling guidelines This document describes the OpenCores HDL modelling guidelines with some examples Brought to You By OpenCores

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Source URL: cdn.opencores.org

Language: English - Date: 2011-06-07 09:12:49
13Increasing Design Productivity Through Core Reuse, Meta-Data Encapsulation, and Synthesis Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent Nelson, Michael Rice, and Mi

Increasing Design Productivity Through Core Reuse, Meta-Data Encapsulation, and Synthesis Adam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent Nelson, Michael Rice, and Mi

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Source URL: www.chrec.org

Language: English - Date: 2013-03-11 16:17:15
141  An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing Nathaniel Rollins, Adam Arnesen, and Michael Wirthlin NSF Center for High-Performance Reconfigurable Computing (CHREC)

1 An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing Nathaniel Rollins, Adam Arnesen, and Michael Wirthlin NSF Center for High-Performance Reconfigurable Computing (CHREC)

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Source URL: www.chrec.org

Language: English - Date: 2013-03-11 16:23:00
15A MULTI-LAYERED XML SCHEMA AND DESIGN TOOL FOR REUSING AND INTEGRATING FPGA IP Adam Arnesen, Nathaniel Rollins, and Michael Wirthlin NSF Center for High-Performance Reconfigurable Computing (CHREC) Dept. of Electrical an

A MULTI-LAYERED XML SCHEMA AND DESIGN TOOL FOR REUSING AND INTEGRATING FPGA IP Adam Arnesen, Nathaniel Rollins, and Michael Wirthlin NSF Center for High-Performance Reconfigurable Computing (CHREC) Dept. of Electrical an

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Source URL: www.chrec.org

Language: English - Date: 2013-03-11 16:16:44
16Microsoft Word - PRESS RELEASE SuperSpeed.doc

Microsoft Word - PRESS RELEASE SuperSpeed.doc

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Source URL: www.usb.org

Language: English - Date: 2011-01-05 20:47:32
17FOR IMMEDIATE RELEASE  NoCustomer Inquiries Information Technology R&D Center

FOR IMMEDIATE RELEASE NoCustomer Inquiries Information Technology R&D Center

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Source URL: www.mitsubishielectric.com

Language: English - Date: 2015-02-03 21:01:52
18Enhancing Trust in Reconfigurable Based Hardware Systems with Tags and Monitors Devu Manikantan Shila, Vivek Venugopalan Cameron D Patterson

Enhancing Trust in Reconfigurable Based Hardware Systems with Tags and Monitors Devu Manikantan Shila, Vivek Venugopalan Cameron D Patterson

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Source URL: eprint.iacr.org

Language: English - Date: 2015-05-07 22:23:51
19TUNITED STATES SECURITIES AND EXCHANGE COMMISSION WASHINGTON, D.CFORM 10-K 

TUNITED STATES SECURITIES AND EXCHANGE COMMISSION WASHINGTON, D.CFORM 10-K 

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Source URL: www.ceva-dsp.com

Language: English - Date: 2014-03-16 13:26:49
20IP Roundtable  September 25, 2012– Mentor Graphics, Fremont, California Warren Savage & Harrison Beasley 1

IP Roundtable September 25, 2012– Mentor Graphics, Fremont, California Warren Savage & Harrison Beasley 1

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Source URL: www.gsaglobal.org

Language: English - Date: 2014-01-22 10:44:05